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description the CXA2021S is a bipolar ic developed as an i 2 c bus control sound processor for tv. this ic implements surround, tone control, balance, volume, mute and agc functions. features i 2 c bus control the agc circuit is adopted to absorb volume differences between input sources and improve the s/n ratio in hearing. absolute maximum ratings supply voltage v cc 14 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 0.9 w recommended operating condition supply voltage 8 to 13 v pin configuration structure bipolar silicon monolithic ic applications tvs ?1 CXA2021S e95319a26 i 2 c bus sound processor for tv sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 22 pin sdip (plastic) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 r-in gnd cl-r ch-r bal tre bass vol rout det2 scl l-in vcc cl-l ch-l vrs hpi hpo ps lout det1 sda
2 CXA2021S block diagram 1 22 l-in r-in 20 19 21 10 13 17 16 agc det 1 agc det 2 150hz hpf det1 det2 vcc ch-l cl-l 9 14 lout rout 11 12 8 5 6 7 3 4 2 15 18 vcc/2 vrs gnd ps sda scl dac bus dec tone vca tone vca bass tre vol bal ps bass tre bal vol i 2 c bus sound processor surround l = l (l r) 1 scr 1 + scr r = r + (l r) 1 scr 1 + scr r = 18k ch-r cl-r
3 CXA2021S pin description (ta = 25 c, v cc = 12v) pin no. symbol voltage equivalent circuit description 1 22 r-in l-in 6v input pins. 2 gnd 0v gnd pin. 1 vcc 10 10k 30k 130 vcc 2 22 3 20 cl-r cl-l 6v pins for connecting external lpf capacitance (bass). vcc 250 11k 130 3 250 11k 5.4k 2 vcc 20 4 19 ch-r ch-l 6v pins for connecting external hpf capacitance (treble). vcc 250 5.7k 130 250 5.7k 6k 4 19 5 6 7 8 bal tre bass vol 4.5v dac output pins. connect lpf capacitance of dac. internal impedance is approximately 20k ? . 5 6 7 8 7.5v vcc 40k 2k 2k 20k 75
4 CXA2021S 9 14 rout lout 6v output pins. 130 5p 84k 500 500 vcc 9 14 10 det2 agc detector output and control pin. vcc 200 200 130 10k 100k 100k 10 11 scl i 2 c bus clock line. 4k vcc 100 50 3k 11k 56k 11 12 sda i 2 c bus data line. 4k vcc 100 50 3k 4.5k 56k 12 pin no. symbol voltage equivalent circuit description
5 CXA2021S 13 det1 7.8v agc detector output. connect capacitance for setting time constant. 13 vcc 40k 2k 15 ps 6v pin for connecting external capacitance of the surround phase shifter. internal impedance is approximately 18k ? . vcc 10 130 18k 18k 15 16 hpo 6v agc hpf output pin. 10k 500 500 vcc 16 17 hpi 6v agc hpf input pin. vcc 10 130 5k 16k 16k 2 vcc 17 pin no. symbol voltage equivalent circuit description
6 CXA2021S 18 vrs 6v v cc reference voltage pin. 2 vcc 30k 1k 30k 16k 16k 30 18 21 v cc 12v power supply pin. pin no. symbol voltage equivalent circuit description
7 CXA2021S control register table slave address = 82h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 volume (00) mute (0) agc (0) bass (00) ? mode (0) ? treble (00) ? balance (00) ? data agc: 0 = off , 1 = on mute: 0 = off , 1 = on (power-on setting value) volume: volume control for both l channel and r channel 00 = minimum value 3f = maximum value mute: mute switch 0 = mute off 1 = mute on (mute state) agc switch 0 = agc off 1 = agc on bass: low-frequency control 00 = minimum value 10 = typical value 1f = maximum value mode: surround switch 0 = surround off 1 = surround on treble: high-frequency control 00 = minimum value 10 = typical value 1f = maximum value balance: balance control for l channel and r channel 00 = l channel minimum, r channel maximum 20 = typical 3f = l channel maximum, r channel minimum
8 CXA2021S electrical characteristics measurement circuit r-in c1 4.7 c3 0.1 c5 4700p c7 4.7 c9 4.7 c11 4.7 c12 4.7 c16 10 rout c14 10 scl r6 220 r5 1meg sda r7 220 c17 4.7 c15 10 lout c13 10 c10 0.1 c8 47 c6 4700p c4 0.1 c2 4.7 l-in 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 r-in gnd cl-r ch-r bal tre bass vol rout det2 scl l-in vcc cl-l ch-l vrs hpi hpo ps lout det1 sda CXA2021S r2 10k r1 10k r3 10k r4 10k ps on s1 tp-ps
9 CXA2021S application circuit r-in c1 4.7 c3 0.1 c5 4700p c7 4.7 c9 4.7 c11 4.7 c12 4.7 c16 10 rout c14 10 scl r2 220 r1 1meg sda r3 220 c17 4.7 c15 10 lout c13 0.1 c10 0.1 c8 47 c6 4700p c4 0.1 c2 4.7 l-in 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 r-in gnd cl-r ch-r bal tre bass vol rout det2 scl l-in vcc cl-l ch-l vrs hpi hpo ps lout det1 sda CXA2021S application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
10 CXA2021S no. measurement item symbol input conditions vol mute agc bass mode tre bal input point input signal sw set to on measure -ment point remarks min. typ. max. unit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 current consumption flat l, r ref, level l, r vol min l, r flat frequency response 100hz flat frequency response 10khz bass boost 100hz treble boost 10khz bass cut 100hz treble cut 10khz balance boost l balance cut l balance boost r balance cut r i cc v f l, r v r l, r v min l, r v lf l, r v hf l, r v bst lf v bst hf v cut lf v cut hf v bal bst l v bal cut l v bal bst r v bal cut r 3f 20 0 20 0010 1f 0 10 010 1f 0 10 20 3f 0 3f l-in r-in 1khz 2.4vrms 100hz 2.4vrms 10khz 2.4vrms 100hz 2.4vrms 10khz 2.4vrms 100hz 2.4vrms 10khz 2.4vrms 1khz 2.4vrms lout rout lout rout ref: input ref: v r l, r 16 2.0 17 1.5 1.5 8.5 8.5 13.5 13.5 0 0 31 0 14 0 0 11 11 11 11 1.2 1.2 50 2.0 11 70 1.5 1.5 13.5 13.5 8.5 8.5 2.0 30 2.0 30 ma db db db db db db db db db db db db db electrical characteristics (ta = 25 c, v cc = 12v)
11 CXA2021S no. vol mute agc bass mode tre bal 15 16 17 18 19 20 21 22 23 24 25 26 27 28 distortion l, r mute l, r cross-talk l r cross-talk r l noise level l, r agc boost l, r agc boost2 l, r agc null l, r agc cut l, r ss dif gain l ss dif gain r ss mix level l ss mix level r dc off-set 1 vdist v mt l, r v ct l, r v ct r, l v noi l, r v gcb l, r v gcb2 l, r v gcn l, r v gcc l, r s dg l s dg r s mx l s mx r do1 3f 0 1 0 0 0 1 0 1 0 1 0 1 0 10 10 0 0 1 0 10 20 l-in r-in l-in r-in l-in r-in l-in r-in ps 1khz 2.4vrms 1khz 10mvrms 1khz 50mvrms 1khz 160mvrms 1khz 2vrms 1khz 2.5vrms 1khz 1.25vrms s1 lout rout rout lout lout rout tp-ps lout rout lout rout ref:input ref: v fr ref: v fl 30khz lpf ref: agc-off (0) ref: agc-off (0) ref: agc-off (0) ref: agc-off (0) 0 5 2.5 24 2 2 3 3 1 2.5 7 0.5 20 0 0 6 6 0 2.0 70 70 70 60 5 10 2 16 2 2 9 9 1 % db db db dbm db db db db db db db db v measurement item symbol input conditions input point remarks min. typ. max. unit input signal sw set to on measure -ment point
12 CXA2021S no. vol mute agc bass mode tre bal 29 30 31 32 33 dc off-set 2 dc off-set 3 dc off-set 4 dc off-set off ss vol min noise l, r do2 do3 do4 do ss l, r v minno l, r 3f 0 00 10 1f 10 0 0 1 0 10 10 0 10 1f 10 20 lout rout ref: mode 0 30khz lpf 1 1 1 150 0 0 0 0 92 1 1 1 150 85 v v v mv dbm measurement item symbol input conditions input point remarks min. typ. max. unit input signal sw set to on measure -ment point
13 CXA2021S agc circuit the agc circuit is incorporated in the input block. when agc is turned on, gain is 0db for small signal input, boosted for medium signal input and reduced for large signal input. the agc circuit can absorb volume differences between input sources. surround circuit l-r signals passing through the phase shifter are added to l channel and r channel each in the opposite phase. the transfer function of the phase shifter is obtained by the following equation: v o = vin where r is internal resistance 18k ? and c is external capacitance. tone circuit bass and treble tone control. bass control characteristic can be determined by external capacitance connected to c l , and treble control characteristic by external capacitance connected to c h . tone control can be performed in 32 steps. balance and volume circuits controls balance and volume in 64 steps each. dac dac circuit for controlling bass, treble, volume and balance. internal impedance is approximately 20k ? . connect external capacitance for lpf. 1 scr 1 + scr
14 CXA2021S tone characteristic 100 1k 10k 20 10 0 10 20 out l, r [db] bass-treble max. bass-treble min. frequency [hz] ch. vs. treble-control (max) 10 1k 10k 2.5 0.0 12.5 15.0 17.5 out l, r [db] frequency [hz] 2.5 5.0 7.5 10.0 100 100k cl. vs. bass-control (max) 10 1k 10k 2.5 0.0 12.5 15.0 17.5 out l, r [db] frequency [hz] 2.5 5.0 7.5 10.0 100 100k 0.047 2200p 470p 4700p 0.047 0.022 0.47 1 0.01 0.1
15 CXA2021S 10 20 30 3f 80 70 60 50 40 30 20 10 0 vol control characteristic bus data [vol] out l, r [db] 10 20 30 3f 80 70 60 50 40 30 20 10 0 balance control characteristic bus data [balance] out l, r [db] 0 out r out l input = 10khz 12 10 8 6 4 2 0 2 4 6 8 10 12 0 4 8 c 10 14 18 1c 1f treble control characteristic bus data [treble] out l, r [db] input = 100hz 12 10 8 6 4 2 0 2 4 6 8 10 12 0 4 8 c 10 14 18 1c 1f bass control characteristic bus data [bass] out l, r [db] 10 100mv 1v 10 100mv 1v out [rms] in [rms] agc characteristic agc = off agc = on
16 CXA2021S package outline unit: mm sony code eiaj code jedec code package structure molding compound lead treatment lead material package mass epoxy resin solder plating copper alloy 22pin sdip (plastic) sdip-22p-01 sdip022-p-0300 0.95g 1.778 11 12 1 22 19.2 0.1 + 0.4 7.62 6.4 0.1 + 0.3 0.25 0.05 + 0.1 0 ? to 15 ? 0.5 0.1 0.9 0.1 + 0.15 3.25 0.2 + 0.15 0.51 min 3.9 0.1 + 0.4 1.all mat surface type. two kinds of package surface: 2.all mirror surface type. sony corporation sony code eiaj code jedec code package structure molding compound lead treatment lead material package mass epoxy resin solder plating copper alloy 22pin sdip (plastic) sdip-22p-01 sdip022-p-0300 0.95g 1.778 11 12 1 22 19.2 0.1 + 0.4 7.62 6.4 0.1 + 0.3 0.25 0.05 + 0.1 0 ? to 15 ? 0.5 0.1 0.9 0.1 + 0.15 3.25 0.2 + 0.15 0.51 min 3.9 0.1 + 0.4 1.all mat surface type. two kinds of package surface: 2.all mirror surface type. lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.

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